Why phase locked loop

This solution might also apply to other similar products or applications. How does a phase-locked loop work? What hardware connections are required for PLL circuits? Solution Phase-locked loop PLL A phase-locked loop PLL is a feedback circuit designed to allow one circuit board to synchronize the phase of its on board clock with an external timing signal.

PLL circuits operate by comparing the phase of an external signal to the phase of a clock signal produced by a voltage controlled crystal oscillator VCXO. Thus, the original reference signal and the new signal are precisely in phase with each other. A good visual example of this is shown in the following figure 1 from the X Series manual.

The concept of phase difference takes this concept a little further. Although the two signals we looked at before have the same frequency, the peaks and troughs do not occur in the same place. There is said to be a phase difference between the two signals. This phase difference is measured as the angle between them. It can be seen that it is the angle between the same point on the two waveforms. In this case a zero crossing point has been taken, but any point will suffice provided that it is the same on both.

This phase difference can also be represented on a circle because the two waveforms will be at different points on the cycle as a result of their phase difference. The phase difference measured as an angle: it is the angle between the two lines from the centre of the circle to the point where the waveform is represented. When there two signals have different frequencies it is found that the phase difference between the two signals is always varying.

The reason for this is that the time for each cycle is different and accordingly they are moving around the circle at different rates. It can be inferred from this that the definition of two signals having exactly the same frequency is that the phase difference between them is constant.

There may be a phase difference between the two signals. This only means that they do not reach the same point on the waveform at the same time. If the phase difference is fixed it means that one is lagging behind or leading the other signal by the same amount, i. A phase locked loop, PLL, is basically of form of servo loop. Although a PLL performs its actions on a radio frequency signal, all the basic criteria for loop stability and other parameters are the same.

Figures 13 through 16 illustrate how this is achieved. In these examples, two PLLs are used to generate frequencies suitable for a 5G systems local oscillator LO in a range between 7. Figure Care needs to be taken with fractional-N PLLs to ensure that spurious tones do not degrade system performance. Integer N PLL.

Fractional-N PLL. Integer N PLL in-band phase noise. Fractional-N PLL in-band phase noise. EVM is similar in scope to integrated phase noise, which considers the noise contribution over a range of offsets. For the 5G system listed earlier, the integration limits are quite wide, starting at 1 kHz and continuing to MHz. EVM can be thought of as a percentage degradation of a perfectly modulated signal from its ideal point expressed as a percentage Figure In a similar manner, integrated phase noise integrates the noise power at different offsets from the carrier and expresses this noise as a dBc number compared to the output frequency.

Modern signal source analyzers will also include these numbers at the push of a button Figure As modulation schemes increase in density, EVM becomes critical. However, since EVM is comprised of various other nonideal parameters due to power amplifier distortion and unwanted mixer products, the integrated noise in dBc is usually defined separately. Phase error visualization. Signal source analyzer plot. VCO blocking specifications are very important in cellular systems that need to account for the presence of strong transmissions.

If a receiver signal is weak, and if the VCO is too noisy, then the nearby transmitter signal can mix down and drown out the wanted signal Figure The illustration in Figure 19 demonstrates how the nearby transmitter kHz away transmitting at —25 dBm power could, if the receiver VCO is noisy, swamp the wanted signal at — dBm. These specifications form part of a wireless communications standard. The blocking specifications directly influence the performance requirement of the VCO. VCO noise blockers.

The next PLL circuit element to be considered in our circuit is the voltage controlled oscillator. With VCOs, a fundamental trade-off between phase noise, frequency coverage, and power consumption is necessary. The higher the quality factor Q of the oscillator, the lower the VCO phase noise is.

However, higher Q circuits have narrower frequency ranges.